1. Field of the Invention
This invention relates to an active matrix board having an addition capacity.
2. Description of the Prior Art
A display pattern is formed on the screen of liquid crystal display devices, EL display devices, plasma display devices, etc., by selectively driving picture element electrodes arranged in a matrix. A voltage is applied between the selected picture element electrode and the opposing electrode positioned opposite the selected picture element electrode so as to optically modulate a display medium disposed therebetween. This optical modulation is observed as the display pattern. One drive method used to drive picture element electrodes is the active-matrix drive method wherein the independent picture element electrodes are arranged in rows and driven by switching elements that are connected with the corresponding picture element electrodes. The switching elements which selectively drive the picture element electrodes are generally thin-film transistor (TFT) elements, metal-insulator-metal (MIM) elements, MOS transistors, diodes, or varistors. Active-matrix drive systems make high-contrast displays possible and are used in liquid crystal television, word processors and computer terminal display devices.
An active matrix board employed in such a display apparatus may be provided with an addition capacity so as to enable sufficient contrast to be obtained. The addition capacity is formed between each pixel electrode and an addition capacity electrode placed on the pixel electrode so as to sandwich an insulating film or the like therebetween.
One example of a conventional active matrix board having an addition capacity is shown in FIG. 3. FIGS. 4 and 5, respectively, are sectional views taken along lines IV'--IV' and V--V in FIG. 3. In this active matrix board, a gate bus line 3 also function as both an addition capacity electrode and an addition capacity line. As shown in FIG. 3, a TFT 20 acting as a switching element is provided in a corner portion of each of the pixel electrodes 11 arranged in a matrix fashion. Each pixel electrode 11 and the corresponding TFT 20 are electrically connected to each other by a drain electrode 17. The TFT 20 and a corresponding source bus line 12 are connected to each other by a source electrode 16.
Each gate bus line 3 comprises a first gate bus line 15 and a second gate bus line 18. A gate electrode 13 of each TFT 20 is branched from the second gate bus line 18. An end of the pixel electrode 11 is layered on the gate bus line 3 so as to sandwich a gate insulating film 5 therebetween at a location opposite to the side where the TFT 20 is disposed on the gate bus line 3 (FIG. 5). In this area, the end of the pixel electrode 11 is layered on both the first gate bus line 15 and the second gate bus line 18. In this board, a portion of each gate bus line also functions as an addition capacity electrode in this way. In other words, an addition capacity 14 is formed by an area in which the end portion of the pixel electrode 11 and the gate bus line 3 are placed in a superposed relation.
The sectional configuration of a region adjacent each TFT 20 will be explained with reference to FIG. 4. On a glass substrate 1 is disposed a gate electrode 13 branched from each second gate bus line 18, with an anode oxide film 4 formed on the gate electrode 13. A gate insulating film 5 is placed over the entire surface of the anode oxide film 4, and a semiconductor film 6 is formed on the gate electrode 13 so as to sandwich the gate insulating film 5 and anode oxide film 4 therebetween. A source electrode 16 and a drain electrode 17 are formed on the semiconductor film 6. The source electrode 16 comprises a first source electrode 7 and a second source electrode 8. The drain electrode 17 comprises a first drain electrode 9 and a second drain electrode 10. A pixel electrode 11 is placed over an end portion of the drain electrode 17.
The sectional configuration of each gate bus line 3 will be explained with reference to FIG. 5. Each gate bus line 15 is formed on the glass substrate 1, and a second gate bus line 18 is formed over the entire surface of the first gate bus line 15. An anode oxide film 4 is formed on the second gate electrode 10 in the same manner as the gate electrode 13. The gate insulating film 5 is placed over the entire surface of the anode oxide film 4. An end of the pixel electrode 11 is placed above the region in which the first gate bus line 15 is formed so as to sandwich the gate insulating film 5 therebetween. As mentioned above, an addition capacity 14 is formed by pixel electrode 11 and a portion of a gate bus line 3 on which the pixel electrode 11 is mounted.
In the active matrix board, each first gate bus line 15 is formed of a low-resistance metal material, such as A1, Mo, W or the like. The use of a metal material having low specific resistance for the first gate bus line 15 of each gate bus line 3 eliminates the possibility of any signal delay being caused on the gate bus line 3 and enables high image quality to be obtained.
On the other hand, however, such a low-resistance metal lacks acid resistance. Therefore, if any slight pinhole is present in a layer formed on the gate bus line 3, the gate bus line 3 may be eroded by an etchant used in a subsequent stage of, for example, the formation of TFT 20. In view of this fact, each second gate bus line 18 is made of a metal material having good acid resistance, such as Ta or the like, to thereby prevent such erosion trouble. That is, the second gate bus line 18 is so formed as to cover the entire surface of the first gate bus line 15, whereby the first gate bus line 15 is protected against the action of the etchant used in the subsequent stage of etching.
However, the trouble with the conventional board is that since the addition capacity 14 is positioned on a stepped portion formed by the first and second gate bus lines 15 and 18, a charge leak is likely to develop between the pixel electrode 11 and the gate bus line 3. In a portion subjected to such a charge leak, the charge holding capability of the addition capacity 14 is deteriorated, with the result that there will be caused display variations which in turn lead to image quality degradation. Once a pixel defect is caused, the image quality is noticeably deteriorated and the production yield of display apparatus will be lowered.